What is clock tree synthesis
Encounter: keep time violation on clkgate
I am trying to get rid of a clkgate timing violation. I have two of these and these are really big violations as you can see in this report:
These violations are due to clock gating, if I understand the documentation well, but there is no additional information on how to resolve these type of violations. The violated paths relate to a clock path between a JTAG and a memory.
I tried using the -clkGateAware option to place the cells differently but it didn't help. I've already tried to compile several times (10x in a row in the hold optimization block), but that didn't solve the problem ...
What can be the cause of such a large violation? Is there an easy option I can use to solve this problem? Can anyone suggest something smart to get rid of this type of clkgate?
EDIT: To make it clearer: My project consists of an ARM M0, two SRAM, a HW Accelerator and an SPI. There is also a JTAG slave to program the memory with the code for the M0.
All of these peripheral devices are connected to the AHB bus and work perfectly. The synthesis is fine with no path of injury. However, when I try to place and route the design it is clock gated to reduce power consumption. This also adds hurtful paths (two). So my question is more related to Encounter and the tweak commands: Can I do something to avoid this broken path?
A simple solution is to slow the clock down. A more complex solution is to use gate types that don't violate set-up time and swap them out if possible. A physical approximation of the route and location could also be an option.
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